----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:56:43 04/25/2012 
-- Design Name: 
-- Module Name:    seven_seg_module - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity seven_seg_module is
	Port (
		clk : in std_logic;
		data : in std_logic_vector(15 downto 0);
		segments : out std_logic_vector(6 downto 0);
		anode : out std_logic_vector(3 downto 0)
	);
end seven_seg_module;

architecture Behavioral of seven_seg_module is

	signal update_pulse : std_logic;


	signal index : std_logic_vector(1 downto 0);
	signal multiplexed_digit_data : std_logic_vector(3 downto 0);
	
	
	constant pulse_terminal_count : natural := 50E6/500;
	signal pulse_count : natural range 0 to pulse_terminal_count-1 := 0;

	component seven_seg_decoder is
		Port (
			data : in std_logic_vector(3 downto 0);
			segments : out std_logic_vector(6 downto 0)
		);
	end component;
	
	component anode_rotator is		
		Port (
			clk : in std_logic;
			update_pulse : in std_logic;
			anode : out std_logic_vector(3 downto 0)
		);
	end component;
		
	component mux
		Port (
			data_in : in std_logic_vector(15 downto 0);
			index : in std_logic_vector(1 downto 0);
			data_out : out std_logic_vector(3 downto 0)
		);
	end component;
	
	component counter
		Port (
			clk : in std_logic;
			update_pulse : in std_logic;
			count : out std_logic_vector(1 downto 0)
		);
	end component;

begin

	process(clk)
	begin
		if rising_edge(clk) then
			if pulse_count = pulse_terminal_count - 1 then
				pulse_count <= 0;
			else
				pulse_count <= pulse_count + 1;
			end if;
		end if;
	end process;
	
	
	with pulse_count select update_pulse <=
		'1' when pulse_terminal_count - 1,
		'0' when others;

	my_seven_seg_decoder : seven_seg_decoder
		port map (
			data => multiplexed_digit_data,
			segments => segments
		);
		
	my_anode_rotator : anode_rotator
		port map (
			clk => clk,
			update_pulse => update_pulse,
			anode => anode
		);
		
	my_index_counter : counter
		port map (
			clk => clk,
			update_pulse => update_pulse,
			count => index
		);
		
	-- Multiplex 
	my_data_mux : mux
		Port map (
			data_in => data,
			index => index,
			data_out => multiplexed_digit_data
		);
	
		
		


end Behavioral;

